Data processors run programs by executing a sequence of individual instructions which perform a desired function. The execution of each individual instruction involves several separate steps or stages. Each instruction can be separated into the steps of fetching an instruction from memory, decoding the fetched instruction, and executing the decoded instruction. Other steps are also possible. Generally, advanced data processors contain dedicated logic for each stage so that several instructions can be "in flight" in the data processor at a given time. A different portion of the data processor will process a different instruction, typically for a single clock cycle, before forwarding the instruction onto the next stage. This design strategy is known as pipelining. Factors such as the microarchitecture of the data processor, clock cycle length, complexity of logic and integration of memory into the data processor can affect the number and length of each stage.
The orderly execution of instructions by the data processor must be interrupted from time to time. For example, an input/output ("I/O") device, such as a modem or hard drive may have data ready that needs to be processed by the data processor. Similarly, a user may press a key on a keyboard. To handle such situations, data processors are provided with interrupt capability.
Numerous interrupt schemes have been devised to date. Typically, several inputs to the data processor (externally or internally generated) are dedicated to interrupt signaling. Each signal corresponds to a different possible interrupt. When a device or process requires service, then the device or process asserts its interrupt line. The data processor then ceases execution of its normal routine and branches to a sequence of instructions that will service the interrupt. The start address of the interrupt service routine is stored in an accessible storage location for this purpose. For instance, if a keyboard generates the interrupt, then the data processor will read a stored value corresponding to the keyboard interrupt line and branch to the instructions beginning at that address. These interrupt service routine instructions might read the pressed key on its data bus and load the value into memory. After the interrupt, the data processor returns to next instruction it would have executed had the interrupt not occurred.
The processing of interrupts is complicated by their number and their flexibility. There are often several classes of interrupts in a single data processor. Each class is accorded an importance relative to each other class. And, if there is more than one interrupt in a class, then the class members are ranked with respect to each other. It is therefore possible for a higher priority interrupt to interrupt a lower priority interrupt. Also, some interrupts are "maskable." When masked, an interrupt is not acted upon by the data processor. However, the masked interrupt must be captured by the data processor for later sampling or "polling."
These and other features of interrupt schemes require the data processor to determine each cycle which is the most important interrupt that is asserted and is not masked, if any. Once the data processor determines the correct interrupt, then it must determine the correct address to which it should branch. Eventually the data processor can begin fetching instructions at the appropriate address. Consequently, servicing interrupts takes a significant amount of processor time. Simultaneously, the data processor must account for the possibility of a second interrupt. This possibility usually requires complex control circuitry. It is desirable to reduce the processing time of interrupts and the complexity of their control circuitry while maintaining their flexibility.